1. Technical Field of the Invention
The present invention relates to a memory device and to a method for operating the same with high rejection of the noise on the high-voltage supply line. This high-voltage supply line may comprise the supply line connected at the output of a voltage-booster circuit generating a boosted voltage for the memory device. In particular, the present invention concerns, without limitation, a nonvolatile multilevel flash memory device with gate-ramp reading.
2. Description of Related Art
As is known, in multilevel flash memories, the data to be stored are encoded using a number of logic levels, each associated to a different threshold voltage of the memory cells.
During the reading step of the multilevel flash memory, a ramp voltage (either continuous or stepwise) is supplied to the gate terminals of the addressed memory cells. The ramp voltage increases between a minimum value and a maximum value. The current flowing in the memory cell is then converted into a voltage, which is supplied to a comparator circuit that compares it with reference values. The datum stored in the cell can be determined on the basis of the voltage that is supplied to the gate terminal of the memory cell and on the basis of the comparator output.
It is also known that memory cells are organized within a memory array and that memory devices are provided with appropriate decoder circuits for decoding the row and column addresses, which enable selection in reading or in modification (programming or erasure) of a particular memory cell belonging to the memory array.
For greater clarity, reference is made to FIG. 1, which illustrates an extremely simplified diagram of a memory device 1 comprising a memory array 2 formed by a plurality of memory cells 3 (of which only one is shown). The memory cell 3 has a gate terminal connected to a wordline WL and a drain terminal connected to a bitline BL. In a manner well known to those skilled in the art, the bitline BL is connected to a column decoder 9 and the wordline WL is connected (through a row decoder not shown) to a ramp generator 7; moreover, the column decoder 9 is connected to a biasing stage 4. A supply circuit 6 is connected to the column decoder 9 and to the ramp generator 7. The supply circuit 6 is generally constituted by a charge pump, is connected at its input to a low-voltage supply line (not shown) of the memory device 1 (having a voltage, for example, of 3 V), and outputs a boosted voltage, for operation of the memory device 1.
In particular, the column decoder 9 comprises a plurality of selection transistors 11 (of which only one is shown), implemented by NMOS or PMOS transistors (known as “pass transistors”), the number of which is linked to the organization and size of the memory array 2, or of the partitions into which the memory array 2 is divided. In detail, the selection transistors 11, when enabled, connect the drain terminal of each memory cell 3 to the biasing stage 4 so as to supply reading or programming biasing voltages, according to the operating step of the memory device 1.
During reading, the ramp generator 7 supplies, on the gate terminal of the memory cell 3, a read ramp voltage, e.g., up to a maximum of 6 V, and the biasing stage 4 supplies, on the drain terminal of the memory cell 3, and through the column decoder 9, a constant voltage, for example of approximately 0.7 V. In particular, for said voltage to be present on the drain terminal of the memory cell 3, the corresponding selection transistors 11 must be driven into conduction with a boosted gate voltage typically around 5 V or 6 V.
As is known, a ripple is usually present on the boosted voltage at the output of the supply circuit 6, which constitutes a noise. While the ramp generator 7 has a high rejection of the noise on the input supply voltage, the ripple on the output of the supply circuit 6 is transferred directly onto the gate terminal of the selection transistors 11. Said noise, on account of the capacitive coupling between the gate terminal and the source and drain terminals of the selection transistor 11, generates a similar noise on the current flowing in the memory cell 3.
Since reading of the memory cell 3 is based, as described, upon the value of the current flowing in the memory cell 3, the noise on the output of the supply circuit 6 can generate reading errors of the data stored in the memory cell 3.
FIG. 2a shows the plot of the current Io flowing in the memory cell 3 during the reading step, and in the presence of a noise on the output of the supply circuit 6, causing a variation of the voltage Vg supplied to the gate terminal of the selection transistor 11 (see FIG. 2b). In particular, it may be noted that a 0.5 V increase of the voltage Vg on the gate terminal of the selection transistor 11 in a time interval of 1 ns causes a transient of 4 ns, wherein the current Io undergoes a peak decrease of 6.5 μA. FIG. 3 shows the frequency domain plot of the noise on the current Io. It is clear that said current variation can effectively cause an error in reading of the datum stored in the memory cell 3.
A need accordingly exists to overcome the shortcomings of the prior art, and in particular to provide a memory with high rejection of the noise on the high-voltage supply line, thus enabling a reduction of the reading errors caused thereby.